1. Field of the Invention
The present invention relates to an LSI testing method and an LSI that is suitably adopted for the LSI testing method. It particularly relates to a method capable of testing a high-speed and highly functional LSI chip easily, reliably and rapidly.
2. Description of the Prior Art
In the conventional practice, employed an LSI (Large Scale Integration) tester has been employed for functional and DC/AC characteristics testing of an LSI chip and for analyzing a fault of the LSI chips as shown in FIG. 1. The LSI tester produces a clock with a basic operation frequency necessary for testing the LSI chip, inputs an operation result of the LSI to the LSI tester, and then outputs an evaluation result to a CRT (Cathode Ray Tube). An equipment having evaluation means except for the tester is called evaluation equipment hereinafter. There are available various kinds of evaluation equipment depending on what is to be evaluated. A high-grade equipment is especially costly. The high-grade tester/evaluation equipment is, in general, the one that can test an LSI chip with clock speeds of greater than 50 MHz.
In a high temperature test of the LSI chip, the LSI tester or the evaluation equipment is connected to a thermostatic chamber so that a high-speed clock or an input signal such as an operation signal is sent to each LSI chip from the LSI tester or the evaluation equipment, and then an output signal of each LSI chip is inputted back to the LSI tester to be evaluated. This test is better known as a BURN-IN test. In the BURN-IN test, a relatively simple evaluation equipment is used since a costly equipment cannot be practically used in, for example, a mass-production line of 10,000 items of LSI chips.
In the above-mentioned LSI testings, the LSI tester and evaluation equipment are equipped with a predetermined pattern generator and a plurality of signal channels so that the evaluation equipment can supply a clock if the clock alone is desired and it can supply a test pattern if some sort of test pattern is required to enable the LSI chip in an operation condition.
However, in the above conventional LSI test method, the clock generated by the LSI test is supplied to the LSI to be tested and evaluated. Therefore, the clock and the test pattern which are supplied from the tester must be adjusted corresponding to the specific clock and test pattern of the LSI chip to be tested, thus requiring much extra time for completing such adjustment.
Further, especially in the BURN-IN test, a the costly evaluation equipment cannot be practically utilized, and thus, a high-speed clock cannot be supplied to a highly functional LSI chip. Hence, a precise test and evaluation cannot be executed at the high-speed clock. Even if a reliable high-speed and costly LSI tester or evaluation equipment is used, further increases of clock frequency are constantly required to meet an ever fast-growing demand in LSI chip capacity especially in terms of clock speed which is becoming fasted and complicated. Therefore, the currently available relatively costly LSI tester or evaluation equipment will soon be somewhat obsolete in that sense, thus, constantly requiring further improvement to the current functional capability of the tester. This fast raises a grave concern over increases in the test cost in terms of manufacturing costs as a whole.